A phase locked loop (PLL) is a frequency feedback circuit that is used to lock a locally generated clock signal to an external reference signal. A PLL is useful in telecommunications equipment and audio/visual equipment that receive a reference signal and require a local clock signal, whose frequency and phase are related (locked) to the received signal, in order to properly decode incoming signals.
In general, a PLL includes a reference frequency generator, a phase and frequency detector (PFD), a charge pump and a voltage controlled oscillator (VCO). The PFD detects the frequency and phase difference between the VCO output frequency (as a feedback signal) and the reference frequency. The PFD outputs a control signal to the charge pump to produce a voltage that is proportional to the frequency and phase difference.
Conventional PLL systems are notoriously noisy during their acquisition and tracking cycles because of the desire to adjust and correct quickly the frequency of the VCO output signal. Hence, there is a need for an improved PLL system that quickly adjusts its frequency output but produces little noise in the process. Additionally, there is a need to accurately determine when the PLL frequency is within a small error range that may be expressed in minute quantities of parts per million (PPM). The present invention addresses such a PLL system.